This invention relates generally to transistors, and more particularly, to a transistor having an integrated gate resistor.
In applications requiring the paralleling of power MOS transistors (whether lateral or vertical devices), the high gain, high frequency characteristics of these devices make them prone to oscillation. In the past, two techniques have been used to reduce unwanted oscillation:
1. The gate geometry may be designed so that its distributed resistance minimizes the occurrence of the oscillations, or PA1 2. A resistor may be placed in series with portions of the gate metallization of the transistor.
While both of these techniques have been found effective, each has certain disadvantages.
The presence of distributed gate resistance has been found to slow the propagation of the gate drive signal across the device when rapid turn on or turn off is required This distributed resistance establishes a minimum device response time which may be unsatisfactory.
The use of an external resistor in series with portions of the gate metallization increases device complexity and make also require additional chip area.